It is well-known that a peak in the electric field at the drain edge of the gate contact can limit the breakdown voltage of FETs. In GaN FETs, the high electric fields in this region also commonly result in electron trapping in surface states and may also result in electron trapping in the buffer, barrier, or passivation layers of the device, resulting in a virtual gate and reducing the on-state current of the device during high-voltage dynamic operation, known as “current collapse” or increased dynamic on-resistance. These issues can be mitigated through the use of field plates, which distribute the electric field over a larger area in the gate-drain region of the device, therefore reducing the peak field intensity. In the prior art high-voltage GaN devices have typically utilized one or more gate or source connected planar field plates. Planar field plates result in a non-optimal electric field profile with one or more peaks, limiting the high-voltage performance of the device.
The prior art includes conventional single field-plate GaN FETs, multiple field-plate GaN FETs, and slant gate FETs.
Y. F. Wu et al. in “30-W/mm GaN HEMTs by Field Plate Optimization”, IEEE Electron Device Letters, Vol. 25, No. 3 (2004) describe a single planar gate-connected field-plate. The primary disadvantage of this approach is a non-optimum electric field profile due to single planar field plate.
Saito et al. in “High Breakdown Voltage AlGaN—GaN Power-HEMT Design and High Current Density Switching Behavior”, IEEE Transactions on Electronic Devices, Vol. 50, No. 12 (2003) describe a single planar source-connected field plate. Field plate design and optimization are limited in this approach due to the planar field-plate and discontinuity between gate and field-plate, resulting in a non-optimal electric field profile.
H. Xing et al. in “High Breakdown Voltage AlGaN—GaN HEMTs Achieved by Multiple Field Plates”, IEEE Electron Device Letters, Vol. 25, No. 4 (2004) describe a planar multiple gate connected field plate structure. The disadvantages include planar field plates and separation between the field plates by supporting dielectric layers, which limits field plate design and results in non-optimum electric field profile, and multiple metallization steps.
Wu et al. in “Wide bandgap transistors with multiple field plates”, US 2009/0267116 A1 (2009) describe several multiple-field-plate GaN FET designs with planar gate and source-connected field plates separated by supporting dielectric layers. The disadvantages of these approaches include planar field-plates and separation between the field plates by supporting dielectric layers, which result in a non-optimal electric field profile.
Parikh et al. in “Wide bandgap transistor devices with field plates” U.S. Pat. No. 7,501,669 B2 (2009) describe several multiple-field-plate GaN FET designs. The disadvantages of these approaches include planar field-plates and separation between the field plates by supporting dielectric layers, which result in a non-optimal electric field profile.
U.S. patent application Ser. No. 14/014,915, filed Aug. 30, 2013 and U.S. patent application Ser. No. 14/014,930, filed Aug. 30, 2013 describe methods of fabricating multi-stepped gate field plates. The stepped field plates have a disadvantage of having a non-optimal electric field profile.
A slant field plate has been suggested as a way to effectively suppress the RF dispersion and the parasitic capacitance. However, fabrication of a slant field plate with a designed shape has been very challenging.
Y. Dora et al. in “High Breakdown Voltage Achieved on AlGaN/GaN HEMTs with Integrated Slant Field Plates”, IEEE Electron Device Letters, Vol. 27, No. 9 (2006) describe a slanted gate field plate to reduce the peak electric field in the device. The disadvantages of this approach include a symmetric gate profile, which increases parasitic Cgs and limits the source-gate spacing, and poor process control over slant gate angle and gate length.
Other references describing slant field plates include: Y. Pei, Z. Chen, D. Brown, S. Keller, S. P. Denbaars, and U. K. Mishra “Deep-Submicrometer AlGaN/GaN HEMTs With Slant Field Plates”, and K. Kobayashi, S. Hatakeyama, T. Yoshida, D. Piedra, T. Palacios, T. Otsuji, and T. Suemitsu “Current Collapse Suppression in AlGaN/GaN HEMTs by Means of Slant Field Plates Fabricated by Multi-layer SiCN”.
In the prior art slant field plate are formed by utilizing the lateral etching property of an isotropic dry etch process. However, a limited lateral etch rate as compared to the vertical etch rate during the isotropic dry etch results in a steep angle in the sloped dielectric structure, which may be typically greater than 45 degrees. This steep angle limits flexibility in field plate design. Also, it is more difficult to control the field plate structure because the angle of the sloped dielectric is controlled by combination of lateral and vertical etch processes.
What is needed is an improved method of fabricating slanted field-plates. The embodiments of the present disclosure answer these and other needs.